Programmable Ramp Generator for SSLAR-ADC
OTT Case 09-016 | Patent Pending
Researchers at the University of Idaho have further advanced the single-slope look-ahead ramp (SSLAR) ADC (see OTT case 08-022) with a programmable SSLAR-ADC. Now code hopping, fall back, and look-ahead operations are no longer fixed options.
The proposed programmable ramp generators can attain variable step sizes that can optimize the image process quality as well as conversion speed in a user-specific manner. This proposed design was fabricated in a 0.5 micrometer 2P3M CMOS process. The parameters and actual chip performance are depicted in the table below.
Parameter |
Value |
---|---|
Process |
0.5 micrometer 2P3M CMOS process |
SSLAR ADC Resolution |
8bit |
Clock Speed |
16MHz |
Supply Voltage |
3.3 Volt |
Layout Area |
0.54 mm2 |
Maximum speed up of SSLAR-ADC |
~6 times |
Maximum speed up of SSLAR-ADC |
~4-5 times |
Maximum speed up of SSLAR-ADC |
~3-4 times |